1. Field of the Invention
The present invention relates to a protection design, particularly to a high voltage open-drain electrostatic discharge (ESD) protection device.
2. Description of the Related Art
The open-drain I/O cell design is used for the application that the external voltage applied on the I/O pad is higher than the internal supply voltage of the I/O cell library. For a high-voltage (HV) open-drain buffer, it does not contain a high-voltage p-channel metal oxide semiconductor field effect transistor (HV PMOSFET, also known as HV PMOS) device connected to the core power line, so that the I/O pads can sustain a voltage higher than the supply voltage. Therefore, it is difficult to have a good ESD protection capability for an open-drain buffer.
Refer to FIG. 1, the conventional multiple channel high voltage open-drain buffer uses the ESD bus to reduce the size of the open-drain buffer, wherein every open-drain channel shares the same ESD clamp element 10 to release the ESD current. As shown in FIG. 2, the ESD protection capability is improved by the HV trigger circuit 12 to efficiently trigger on the ESD clamp element 10 when an ESD event appears on the open-drain I/O pad. The HV trigger circuit 12 is generally composed of a resistor, a capacitor, and a HV inverter. The HV inverter includes a HV PMOS and a high-voltage n-channel metal oxide semiconductor field effect transistor (HV NMOSFET, also known as HV NMOS). When an ESD event occurs, the HV trigger circuit 12 fully turns on the ESD clamp element 10 to provide a lower impedance ESD discharging path to bypass the ESD current. However, the original open-drain I/O cell does not include a HV PMOS, therefore, the mask layer number will be increased by taking an additional HV PMOS of the HV inverter, which means that the cost of the IC fabrication process is increased.
To overcome the abovementioned problems, the present invention provides a new HV open-drain ESD protection design, so as to solve the abovementioned problems of the prior art.